The ever increasing power density of integrated circuits (ICs) has become a crucial limiting factor in preventing the continued growth of ICs in accordance with Moore's Law. For many years, significant effort has been applied to overcome the Boltzmann tyranny, i.e., to implement a 60-mV/decade subthreshold slope (SS) at room temperature.
Meanwhile, alternatives to complementary metal-oxide semiconductor (CMOS) devices have been proposed and studied, including tunnel field-effect transistors (TFETs), nano electro-mechanical system (NEMS), feedback field-effect transistors (FBFETs), etc.
Recently, ferroelectric materials for CMOS applications have also been proposed, and negative capacitance in ferroelectric capacitors formed of the ferroelectric materials has been experimentally demonstrated. That is, it was experimentally demonstrated that the two different electric polarization states of ferroelectric materials can lead to sudden increases in the drain current (ID) of CMOS devices. For example, as an external voltage is applied to a ferroelectric negative capacitor, the negative capacitance in the ferroelectric negative capacitor is explicitly revealed by phase transition from an initial polarization state to an alternate state caused by the movement of the dipoles inside the ferroelectric layer.
However, in order to apply the ferroelectric negative capacitor to the industry, when the ferroelectric negative capacitor is used as a switching device for logic applications, a negative effect of a hysteresis window on the input transfer characteristics of the switching device needs to be improved.